MC912D60ACPVE8 Datasheet, PDF (266/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
15.4.1 Data Format
The serial data format requires the following conditions:
• An idle-line in the high state before transmission or reception of a
message.
• A start bit (logic zero), transmitted or received, that indicates the
start of each character.
• Data that is transmitted or received least significant bit (LSB) first.
• A stop bit (logic one), used to indicate the end of a frame. (A frame
consists of a start bit, a character of eight or nine data bits and a
stop bit.)
• A BREAK is defined as the transmission or reception of a logic
zero for one frame or more.
• This SCI supports hardware parity for transmit and receive.
15.4.2 SCI Baud Rate Generation
The basis of the SCI baud rate generator is a 13-bit modulus counter.
This counter gives the generator the flexibility necessary to achieve a
reasonable level of independence from the CPU operating frequency
and still be able to produce standard baud rates with a minimal amount
of error. The clock source for the generator comes from the M Clock.
Technical Data
266
Table 15-1. Baud Rate Generation
Desired
SCI Baud Rate
110
300
600
1200
2400
4800
9600
14400
19200
38400
BR Divisor for
M = 4.0 MHz
2273
833
417
208
104
52
26
17
13
—
BR Divisor for
M = 8.0 MHz
4545
2273
833
417
208
104
52
35
26
13
Multiple Serial Interface
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor