MC912D60ACPVE8 Datasheet, PDF (130/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

I/O Ports with Key Wake-up
Pull-up/down status is selected by PGUPD and PHUPD input pins: pull-
up when PxUPD pin is high, pull-down when PxUPD pin is low. On
80QFP these pins are tied internally so that KWG4 is pull-up and KWH4
is pull-down.
Default register addresses, as established after reset, are indicated in
the following descriptions. For information on re-mapping the register
block, refer to Operating Modes and Resource Mapping.
10.3 Key Wake-up and Port Registers
Bit 7
6
PG7
PG6
RESET:
—
—
Alt. Pin
Function
—
KWG6
PORTG — Port G Register
5
PG5
—
KWG5
4
PG4
—
KWG4
3
PG3
—
KWG3
Read and write anytime.
2
PG2
—
KWG2
1
PG1
—
KWG1
Bit 0
PG0
—
KWG0
$0028
Bit 7
6
PH7
PH6
RESET:
—
—
Alt. Pin
Function
KWH7
KWH6
PORTH — Port H Register
5
PH5
—
KWH5
4
PH4
—
KWH4
3
PH3
—
KWH3
Read and write anytime.
2
PH2
—
KWH2
1
PH1
—
KWH1
Bit 0
PH0
—
KWH0
$0029
Technical Data
130
I/O Ports with Key Wake-up
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor