MC912D60ACPVE8 Datasheet, PDF (233/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
Timer Registers
At the same time the pulse accumulator is cleared.
14.3.3 Modulus Down-Counter
The modulus down-counter can be used as a time base to generate a
periodic interrupt. It can also be used to latch the values of the IC
registers and the pulse accumulators to their holding registers.
The action of latching can be programmed to be periodic or only once.
14.4 Timer Registers
Input/output pins default to general-purpose I/O lines until an internal
function which uses that pin is specifically enabled. The timer overrides
the state of the DDR to force the I/O state of each associated port line
when an output compare using a port line is enabled. In these cases the
data direction bits will have no affect on these lines.
When a pin is assigned to output an on-chip peripheral function, writing
to this PORTT bit does not affect the pin but the data is stored in an
internal latch such that if the pin becomes available for general-purpose
output the driven level will be the last value written to the PORTT bit.
Bit 7
6
5
4
IOS7
IOS6
IOS5
IOS4
RESET:
0
0
0
0
TIOS — Timer Input Capture/Output Compare Select
3
IOS3
0
2
IOS2
0
1
IOS1
0
Bit 0
IOS0
0
$0080
Read or write anytime.
IOS[7:0] — Input Capture or Output Compare Channel Configuration
0 = The corresponding channel acts as an input capture
1 = The corresponding channel acts as an output compare.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Enhanced Capture Timer
Technical Data
233