MC912D60ACPVE8 Datasheet, PDF (346/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
AM7 – AM0 — Acceptance Mask Bits
If a particular bit in this register is cleared this indicates that the
corresponding bit in the identifier acceptance register must be the same
as its identifier bit, before a match is detected. The messageis accepted
if all such bits match. If a bit is set, it indicates that the state of the
corresponding bit in the identifier acceptance register does not affect
whether or not the message is accepted.
Bit description:
0 = Match corresponding acceptance code register and identifier
bits.
1 = Ignore corresponding acceptance code register bit.
NOTE: The CIDMR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
17.13.15 msCAN12 Port CAN Control Register (PCTLCAN)
Bit 7
6
5
4
3
2
1
Bit 0
PCTLCAN R
0
0
0
0
0
0
PUPCAN RDPCAN
$013D W
RESET
0
0
0
0
0
0
0
0
The following bits control pins 7 through 2 of Port CAN. Pins 1 and 0 are
reserved for the RxCan (input only) and TxCan (output only) pins.
PUPCAN — Pull-Up Enable Port CAN
0 = Pull mode disabled for Port CAN.
1 = Pull mode enabled for Port CAN.
In 80QFP all PortCAN[2:7] pins should either be defined as outputs or
have their pull-ups enabled.
RDPCAN — Reduced Drive Port CAN
0 = Reduced drive disabled for Port CAN.
1 = Reduced drive enabled for Port CAN.
Technical Data
346
MSCAN Controller
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor