MC912D60ACPVE8 Datasheet, PDF (243/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
Timer Registers
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC6 — Timer Input Capture/Output Compare Register 6
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC7 — Timer Input Capture/Output Compare Register 7
1
Bit 0
9
Bit 8
1
Bit 0
$009C–$009D
1
Bit 0
9
Bit 8
1
Bit 0
$009E–$009F
Depending on the TIOS bit for the corresponding channel, these
registers are used to latch the value of the free-running counter when
a defined transition is sensed by the corresponding input capture
edge detector or to trigger an output action for output compare.
Read anytime. Write anytime for output compare function. Writes to
these registers have no meaning or effect during input capture. All
timer input capture/output compare registers are reset to $0000.
BIT 7
6
5
4
0
PAEN PAMOD PEDGE
RESET:
0
0
0
0
PACTL — 16-Bit Pulse Accumulator A Control Register
3
CLK1
0
2
CLK0
0
1
PAOVI
0
BIT 0
PAI
0
$00A0
16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit
pulse accumulators PAC3 and PAC2.
When PAEN is set, the PACA is enabled. The PACA shares the input pin
with IC7.
Read: any time
Write: any time
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Enhanced Capture Timer
Technical Data
243