MC912D60ACPVE8 Datasheet, PDF (242/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
TOF — Timer Overflow Flag
Set when 16-bit free-running timer overflows from $FFFF to $0000.
This bit is cleared automatically by a write to the TFLG2 register with
bit 7 set. (See also TCRE control bit explanation.)
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC0 — Timer Input Capture/Output Compare Register 0
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC1 — Timer Input Capture/Output Compare Register 1
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC2 — Timer Input Capture/Output Compare Register 2
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC3 — Timer Input Capture/Output Compare Register 3
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC4 — Timer Input Capture/Output Compare Register 4
Bit 7
6
5
4
3
2
Bit 15
14
13
12
11
10
Bit 7
6
5
4
3
2
TC5 — Timer Input Capture/Output Compare Register 5
1
Bit 0
9
Bit 8
1
Bit 0
$0090–$0091
1
Bit 0
9
Bit 8
1
Bit 0
$0092–$0093
1
Bit 0
9
Bit 8
1
Bit 0
$0094–$0095
1
Bit 0
9
Bit 8
1
Bit 0
$0096–$0097
1
Bit 0
9
Bit 8
1
Bit 0
$0098–$0099
1
Bit 0
9
Bit 8
1
Bit 0
$009A–$009B
Technical Data
242
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor