MC912D60ACPVE8 Datasheet, PDF (339/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Control Registers
RXFIE — Receiver Full Interrupt Enable
0 = No interrupt is generated from this event.
1 = A receive buffer full (successful message reception) event
results in a receive interrupt.
NOTE: The CRIER register is held in the reset state when the SFTRES bit in CMCR0
is set.
17.13.8 msCAN12 Transmitter Flag Register (CTFLG)
The Abort Acknowledge flags are read only. The Transmitter Buffer Empty
flags are read and clear only. A flag can be cleared by writing a 1 to the
corresponding bit position. Writing a zero has no effect on the flag setting.
The Transmitter Buffer Empty flags each have an associated interrupt
enable bit in the CTCR register. A hard or soft reset resets the register.
CTFLG R
$0106 W
RESET
Bit 7
0
0
6
5
4
3
ABTAK2 ABTAK1 ABTAK0
0
2
TXE2
1
TXE1
Bit 0
TXE0
0
0
0
0
1
1
1
ABTAK2 – ABTAK0 — Abort Acknowledge
This flag acknowledges that a message has been aborted due to a
pending abort request from the CPU. After a particular message
buffer has been flagged empty, this flag can be used by the
application software to identify whether the message has been
aborted successfully or has been sent in the meantime. The ABTAKx
flag is cleared implicitly whenever the corresponding TXE flag is
cleared.
0 = The massage has not been aborted, thus has been sent out.
1 = The message has been aborted.
TXE2 – TXE0 —Transmitter Buffer Empty
This flag indicates that the associated transmit message buffer is empty,
thus not scheduled for transmission. The CPU must handshake (clear)
the flag after a message has been set up in the transmit buffer and is due
for transmission. The msCAN12 sets the flag after the message has been
sent successfully. The flag is also set by the msCAN12 when the
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
339