MC912D60ACPVE8 Datasheet, PDF (156/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Clock Functions
11.6.15 PLL Register Descriptions
Bit 7
6
0
0
RESET:
0
0
SYNR — Synthesizer Register
5
SYN5
0
4
SYN4
0
3
SYN3
0
2
SYN2
0
1
SYN1
0
Bit 0
SYN0
0
$0038
Read anytime, write anytime, except when BCSP = 1 (PLL selected as
bus clock).
If the PLL is on, the count in the loop divider (SYNR) register effectively
multiplies up the bus frequency from the PLL reference frequency by
SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution
should be used not to exceed the maximum rated operating frequency
for the CPU.
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
REFDV2 REFDV1 REFDV0
RESET:
0
0
0
0
0
0
0
0
REFDV — Reference Divider Register
$0039
Read anytime, write anytime, except when BCSP = 1.
The reference divider bits provides a finer granularity for the PLL
multiplier steps. The reference frequency is divided by REFDV + 1.
Bit 7
6
5
4
3
2
1
Bit 0
TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0
RESET:
0
0
0
0
0
0
0
0
CGTFLG — Clock Generator Test Register
Always reads zero, except in test modes.
$003A
Technical Data
156
Clock Functions
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor