MC912D60ACPVE8 Datasheet, PDF (441/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Appendix: Changes from MC68HC912D60
Significant changes from the MC68HC912D60 (non-suffix device)
22.2.7.3 Additional Features
ATD flexibility has been increased with additional signed result, data
justification, single conversion selection and results location FIFO
features.
The DJM bit has been added to ATDxCTL2 register. Default values are
compatible with MC68HC912D60 functionality.
FIFO & S1C bits have been added to ATDxCTL3 register. Default values
are compatible with MC68HC912D60 functionality.
22.2.7.4 S8CM bit
Bit S8CM in ATDxCTL5 is renamed S8C. Functionality is compatible
with S8CM but can now be modified by the new S1C bit in ATDxCTL3.
The default is compatible with MC68HC912D60 functionality.
22.2.7.5 AWAI bit
Bit AWAI in ATDxCTL2 is renamed ASWAI, compatible with
M68HC912DT128A. Functionality is unchanged.
22.2.7.6 Writing to ATDxCTL4
Writing to ATDxCTL4 aborts any ongoing conversion sequence and
initiates a new conversion sequence. Previously it only aborted ongoing
sequences leaving the ATD in idle mode (no conversion sequences
being processed). Writing to ATDxCTL2 or ADTxCTL3 also does not
abort an ongoing conversion sequence. Previously writing these
registers also aborted any ongoing sequence leaving the ATD in idle
mode .
This is unlikely to be a compatibility issue as applications mostly write
these registers to configure the ATD, closely followed by a write to
ATDxCTL5 to initiate a new conversion sequence which does abort any
ongoing conversion sequence and resets the appropriate flags.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Appendix: Changes from MC68HC912D60
Technical Data
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