MC912D60ACPVE8 Datasheet, PDF (337/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Control Registers
BOFFIF — BUSOFF Interrupt Flag
This flag is set when the msCAN12 goes into BUSOFF status, due to
the Transmit Error counter exceeding 255. It cannot be cleared before
the msCAN12 has monitored 128 times 11 consecutive recessive bits
on the bus. If not masked, an Error interrupt is pending while this flag
is set.
0 = No BUSOFF status has been reached.
1 = msCAN12 went into BUSOFF status.
OVRIF — Overrun Interrupt Flag
This flag is set when a data overrun condition occurrs. If not masked,
an Error interrupt is pending while this flag is set.
0 = No data overrun has occurred.
1 = A data overrun has been detected.
RXF — Receive Buffer Full
The RXF flag is set by the msCAN12 when a new message is
available in the foreground receive buffer. This flag indicates whether
the buffer is loaded with a correctly received message. After the CPU
has read that message from the receive buffer, the RXF flag must be
handshaken (cleared) in order to release the buffer. A set RXF flag
prohibits the exchange of the background receive buffer into the
foreground buffer. If not masked, a Receive interrupt is pending while
this flag is set.
0 = The receive buffer is released (not full).
1 = The receive buffer is full. A new message is available.
WARNING: To ensure data integrity, no registers of the receive buffer shall be read
while the RXF flag is cleared.
NOTE: The CRFLG register is held in the reset state when the SFTRES bit in
CMCR0 is set.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
337