MC912D60ACPVE8 Datasheet, PDF (33/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Central Processing Unit
Data Types
Condition Code Register (CCR) contains five status indicators, two
interrupt masking bits, and a STOP disable bit. The five flags are half
carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The
half-carry flag is used only for BCD arithmetic operations. The N, Z, V,
and C status bits allow for branching based on the results of a previous
operation.
After a reset, the CPU fetches a vector from the appropriate address and
begins executing instructions. The X and I interrupt mask bits are set to
mask any interrupt requests. The S bit is also set to inhibit the STOP
instruction.
2.4 Data Types
The CPU12 supports the following data types:
• Bit data
• 8-bit and 16-bit signed and unsigned integers
• 16-bit unsigned fractions
• 16-bit addresses
A byte is eight bits wide and can be accessed at any byte location. A
word is composed of two consecutive bytes with the most significant
byte at the lower value address. There are no special requirements for
alignment of instructions or operands.
2.5 Addressing Modes
Addressing modes determine how the CPU accesses memory locations
to be operated upon. The CPU12 includes all of the addressing modes
of the M68HC11 CPU as well as several new forms of indexed
addressing. Table 2-1 is a summary of the available addressing modes.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Central Processing Unit
Technical Data
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