MC912D60ACPVE8 Datasheet, PDF (48/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
3.5.6 Mode Select (SMODN, MODA, and MODB)
The state of these pins during reset determine the MCU operating mode.
After reset, MODA and MODB can be configured as instruction queue
tracking signals IPIPE0 and IPIPE1. MODA and MODB have active pull-
downs during reset.
The SMODN pin has an active pull-up when configured as input. This pin
can be used as BKGD or TAGHI after reset.
3.5.7 Single-Wire Background Mode Pin (BKGD)
The BKGD pin receives and transmits serial background debugging
commands. A special self-timing protocol is used. The BKGD pin has an
active pull-up when configured as input; BKGD has no pull-up control.
Refer to Development Support.
3.5.8 External Address and Data Buses (ADDR[15:0] and DATA[15:0])
External bus pins share function with general-purpose I/O ports A and B.
In single-chip operating modes, the pins can be used for I/O; in
expanded modes, the pins are used for the external buses.
In expanded wide mode, ports A and B are used for multiplexed 16-bit
data and address buses. PA[7:0] correspond to
ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].
In expanded narrow mode, ports A and B are used for the16-bit address
bus, and an 8-bit data bus is multiplexed with the most significant half of
the address bus on port A. In this mode, 16-bit data is handled as two
back-to-back bus cycles, one for the high byte followed by one for the
low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or
DATA[7:0], depending on the bus cycle. The state of the address pin
should be latched at the rising edge of E. To allow for maximum address
setup time at external devices, a transparent latch should be used.
Technical Data
48
Pinout and Signal Descriptions
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor