MC912D60ACPVE8 Datasheet, PDF (390/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Development Support
CLKSW — BDMCLK Clock Switch
0 = BDM system operates with BCLK.
1 = BDM system operates with ECLK.
The WRITE_BD_BYTE@FF01 command that changes CLKSW
including 150 cycles after the data portion of the command should be
timed at the old speed. Beginning with the start of the next BDM
command, the new clock can be used for timing BDM communications.
If ECLK rate is slower than BDMCLK rate, CLKSW is ignored and BDM
system is forced to operate with ECLK.
19.4.5.2 INSTRUCTION - Hardware Instruction Decode
The INSTRUCTION register is written by the BDM hardware as a result
of serial data shifted in on the BKGD pin. It is readable and writable in
Special Peripheral mode on the parallel bus. It is discussed here for two
conditions: when a hardware command is executed and when a
firmware command is executed.
Read and write: all modes
The hardware clears the INSTRUCTION register if 512 BDMCLK cycles
occur between falling edges from the host.
BIT 7
6
5
4
3
2
1
BIT 0
H/F
DATA
R/W
BKGND
W/B
BD/U
0
0
RESET:
0
0
0
0
0
0
0
0
INSTRUCTION — BDM Instruction Register (hardware command explanation)
$FF00
The bits in the BDM instruction register have the following meanings
when a hardware command is executed.
H/F — Hardware/Firmware Flag
0 = Firmware command
1 = Hardware command
Technical Data
390
Development Support
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor