MC912D60ACPVE8 Datasheet, PDF (15/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Technical Data — MC68HC912D60A
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MC68HC912D60A 112-pin QFP Block Diagram . . . . . . . . . . . 29
MC68HC912D60A 80-pin QFP Block Diagram . . . . . . . . . . . . 30
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Pin Assignments in 112-pin TQFP for MC68HC912D60A . . . . 38
112-pin TQFP Mechanical Dimensions (case no987) . . . . . . . 39
Pin Assignments in 80-pin QFP for MC68HC912D60A . . . . . . 40
80-pin QFP Mechanical Dimensions (case no841B) . . . . . . . . 41
PLL Loop FIlter Connections . . . . . . . . . . . . . . . . . . . . . . . . . . 43
External Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . .45
MC68HC912D60A Memory Map . . . . . . . . . . . . . . . . . . . . . . . 83
Access Type vsBus Control Pins . . . . . . . . . . . . . . . . . . . . . . . 86
STOP Key Wake-up Filter (falling edge trigger) timing. . . . . . 135
Internal Clock Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . 139
PLL Functional Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Clock Loss during Normal Operation . . . . . . . . . . . . . . . . . . . 144
No Clock at Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . 146
STOP Exit and Fast STOP Recovery . . . . . . . . . . . . . . . . . . . 149
Clock Generation Chain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Clock Chain for SCI0, SCI1, RTI, COP. . . . . . . . . . . . . . . . . . 164
Clock Chain for ECT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Clock Chain for MSCAN, SPI, ATD0, ATD1 and BDM . . . . . . 166
MC68HC912D60A Colpitts Oscillator Architecture. . . . . . . . . 177
MC68HC912D60C Colpitts Oscillator Architecture. . . . . . . . . 180
MC68HC912D60C Crystal with DC Blocking Capacitor . . . . . 192
MC68HC912D60P Pierce Oscillator Architecture. . . . . . . . . . 195
Block Diagram of PWM Left-Aligned Output Channel . . . . . . 208
Block Diagram of PWM Center-Aligned Output Channel . . . . 209
PWM Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Timer Block Diagram in Latch Mode. . . . . . . . . . . . . . . . . . . .225
Timer Block Diagram in Queue Mode. . . . . . . . . . . . . . . . . . . 226
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
List of Figures
Technical Data
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