MC912D60ACPVE8 Datasheet, PDF (361/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
ATD Registers
exited, the ATD module powers up and continues operation. The
module is not reset; the register file is not reinitialized; the conversion
sequence is not restarted.
When the module comes out of wait, it is recommended that a
stabilization delay ( t_SR) is allowed before new conversions are
started.
DJM — Result Register Data Justification Mode
0 = Left justified mode
1 = Right justified mode
For 10-bit resolution, left justified mode maps a result register into
data bus bits 6 through 15; bit 15 is the MSB. In right justified mode,
the result registers maps onto data bus bits 0 through 9; bit 9 is the
MSB.
For 8-bit resolution, left justified mode maps a result into the high byte
(bits 8 though 15; bit 15 is the MSB). Right justified maps a result into
the low byte (bits 0 through 7; bit 7 is the MSB).
Table 18-1 summarizes the result data formats available and how
they are set up using the control bits.
Table 18-2 illustrates left justified output codes for an input signal
range between 0 and 5.1 Volts.
RES10
0
0
1
1
DJM
0
1
0
1
Result Data Formats
Description and Bus Bit Mapping
8-bit/left justified - bits 8-15
8-bit/right justified - bits 0-7
10-bit/left justified - bits 6-15
10-bit/right justified - bits 0-9
Table 18-1. Result Data Formats Available
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Analog-to-Digital Converter
Technical Data
361