MC912D60ACPVE8 Datasheet, PDF (341/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Control Registers
TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable
0 = No interrupt will be generated from this event.
1 = A transmitter empty (transmit buffer available for transmission)
event will result in a transmitter empty interrupt.
NOTE: The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
17.13.10 msCAN12 Identifier Acceptance Control Register (CIDAC)
CIDAC R
$0108 W
RESET
Bit 7
0
0
6
5
4
3
2
1
Bit 0
0
0
IDHIT2
IDHIT1
IDHIT0
IDAM1
IDAM0
0
0
0
0
0
0
0
IDAM1 – IDAM0 — Identifier Acceptance Mode
The CPU sets these flags to define the identifier acceptance filter
organisation (see Identifier Acceptance Filter). Table 17-8
summarizes the different settings. In Filter Closed mode no
messages are accepted such that the foreground buffer is never
reloaded.
Table 17-9. Identifier Acceptance Mode Settings
IDAM1
0
0
1
1
IDAM0
0
1
0
1
Identifier Acceptance Mode
Two 32 bit Acceptance Filters
Four 16 bit Acceptance Filters
Eight 8 bit Acceptance Filters
Filter Closed
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
341