MC912D60ACPVE8 Datasheet, PDF (89/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Bus Control and Input/Output
Registers
BIT 7
6
5
4
3
2
1
BIT 0
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
RESET:
—
—
—
—
—
—
—
—
Alt. Pin
Function
DBE or
ECLK or
CAL
MODB or
IPIPE1 or
CGMTST
MODA or
IPIPE0
LSTRB or
ECLK BDTAGL or R/W
TAGLO
IRQ
XIRQ
PORTE — Port E Register
$0008
This register is associated with external bus control signals and interrupt
inputs, including data bus enable (DBE), mode select (MODB/IPIPE1,
MODA/IPIPE0), ECLK, size (LSTRB), read/write (R/W), IRQ, and XIRQ.
When the associated pin is not used for one of these specific functions,
the pin can be used as general-purpose I/O. The port E assignment
register (PEAR) selects the function of each pin. DDRE determines the
primary direction of each port E pin when configured to be general-
purpose I/O.
Some of these pins have software selectable pull-ups (DBE, LSTRB,
R/W, IRQ, and XIRQ). A single control bit enables the pull-ups for all
these pins which are configured as inputs.
This register is not in the map in peripheral mode or expanded modes
when the EME bit is set.
Read and write anytime.
Bit 7
6
5
4
3
2
1
Bit 0
DDE7
DDE6
DDE5
DDE4
DDE3
DDE2
0
0
RESET:
0
0
0
0
0
0
0
0
DDRE — Port E Data Direction Register
$0009
This register determines the primary direction for each port E pin
configured as general-purpose I/O.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Bus Control and Input/Output
Technical Data
89