MC912D60ACPVE8 Datasheet, PDF (208/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pulse Width Modulator
possible to know where the count is with respect to the duty value and
software can be used to make adjustments by turning the enable bit off
and on.
The four PWM channel outputs share general-purpose port P pins.
Enabling PWM pins takes precedence over the general-purpose port.
When PWM channels are not in use, the port pins may be used for
discrete input/output.
CLOCK SOURCE
(ECLK or Scaled ECLK)
GATE
(CLOCK EDGE SYNC)
PWCNTx
RESET
CENTR = 0
UP/DOWN
8-BIT COMPARE =
PWDTYx
PWENx _SYNC
PPOL = 0
8-BIT COMPARE =
PWPERx
FROM PORT P
DATA REGISTER
S
Q _MUX
Q
R
PPOLx
MUX
TO PIN
DRIVER
PPOL = 1
PWDTY
PWPER
Figure 13-1. Block Diagram of PWM Left-Aligned Output Channel
Technical Data
208
Pulse Width Modulator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor