MC912D60ACPVE8 Datasheet, PDF (299/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Freescale Interconnect Bus
SCI0/MI Bus registers
Bit 7
6
5
4
—
—
RDRF
—
RESET:
1
1
0
0
SC0SR1 — MI Bus Status Register 1
3
2
OR
NF
0
0
1
Bit 0
—
—
0
0
$00C4
The bits in these registers are set by various conditions in the MI Bus
hardware and are automatically cleared by special acknowledge
sequences. The receive related flag bits in SC0SR1 (RDRF, OR and
NF) are all cleared by a read of this register followed by a read of the
transmit/receive data register low byte. However, only those bits
which were set when SC0SR1 was read will be cleared by the
subsequent read of the transmit/receive data register low byte.
Read anytime (used in auto clearing mechanism). Write has no
meaning or effect.
RDRF — Receive Data Register Full Flag
0 = Contents of the receiver shift register have not been transferred
to the receiver data register.
1 = Contents of the receiver serial shift register have been
transferred to the receiver data register.
The EOF (end-of-frame) during an MI Bus pull-field is a continuous
square wave, which will result in multiple RDRFs. This may be dealt
with in any of the following ways:
– By clearing the RIE mask, ignoring unneeded RDRFs, initiating
a push field, waiting for TDRE⁽¹⁾ and then clearing the RDRF
– By clearing the RE bit when a pull field is complete, followed by
setting the RE bit after the TDRE¹ flag associated with the next
push field is asserted.
– By disabling the MI Bus.
1. Note that TDRE and TC will both behave in the same way as during normal SCI transmissions.
The MI Bus will still be receiving when the TC bit becomes set, hence any queued transmission
will not start until the current pull field has finished. See also Register Descriptions.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Freescale Interconnect Bus
Technical Data
299