MC912D60ACPVE8 Datasheet, PDF (43/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
Power Supply Pins
3.4.5 V_DDPLL, V_SSPLL
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed independently.
NOTE:
The VSSPLL pin should always be grounded even if the PLL is not used.
The VDDPLL pin should not be left floating. It is recommended to
connect the VDDPLL pin to ground if the PLL is not used.
3.4.6 XFC
PLL loop filter. Please see Appendix: CGM Practical Aspects for
information on how to calculate PLL loop filter elements. Any current
leakage on this pin must be avoided.
VDDPLL
C₀
MCU
R₀
C_a
XFC
Figure 3-5. PLL Loop FIlter Connections
If VDDPLL is connected to VSS (this is normal case), then the XFC pin
should either be left floating or connected to VSS (never to VDD). If
VDDPLL is tied to VDD but the PLL is switched off (PLLON bit cleared),
then the XFC pin should be connected preferably to VDDPLL (i.e. ready
for VCO minimum frequency).
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pinout and Signal Descriptions
Technical Data
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