MC912D60ACPVE8 Datasheet, PDF (285/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
Port S
some slave devices are very simple and either accept data from the
master without returning data to the master or pass data to the master
without requiring data from the master.
15.6 Port S
In all modes, port S bits PS[7:0] can be used for either general-purpose
I/O, or with the SCI and SPI subsystems. During reset, port S pins are
configured as high-impedance inputs (DDRS is cleared).
PORTS — Port S Data Register
Pin
Function
Bit 7
PS7
SS
CS
6
PS6
SCK
5
PS5
MOSI
MOMI
4
PS4
MISO
SISO
3
PS3
TXD1
2
PS2
RXD1
1
PS1
TXD0
Bit 0
PS0
RXD0
$00D6
Read anytime (inputs return pin level; outputs return pin driver input
level). Write data stored in internal latch (drives pins only if configured for
output). Writes do not change pin state when pin configured for SPI or
SCI output.
After reset all bits are configured as general-purpose inputs.
Port S shares function with the on-chip serial systems (SPI and SCI0/1).
Bit 7
6
5
DDS7
DDS6
DDS5
RESET:
0
0
0
DDRS — Data Direction Register for Port S
4
DDS4
0
3
DDS3
0
2
DDS2
0
1
DDS1
0
Bit 0
DDS0
0
$00D7
Read or write anytime.
After reset, all general-purpose I/O are configured for input only.
0 = Configure the corresponding I/O pin for input only
1 = Configure the corresponding I/O pin for output
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Multiple Serial Interface
Technical Data
285