MC912D60ACPVE8 Datasheet, PDF (238/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
Table 14-1. Compare Result Output Action
OMn
0
0
1
1
OLn
0
1
0
1
Action
Timer disconnected from output pin logic
Toggle OCn output line
Clear OCn output line to zero
Set OCn output line to one
To operate the 16-bit pulse accumulators A and B (PACA and PACB)
independently of input capture or output compare 7 and 0 respectively
the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn
= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.
Bit 7
6
5
EDG7B EDG7A EDG6B
RESET:
0
0
0
TCTL3 — Timer Control Register 3
4
EDG6A
0
3
EDG5B
0
2
EDG5A
0
1
EDG4B
0
Bit 0
EDG4A
0
$008A
Bit 7
6
5
EDG3B EDG3A EDG2B
RESET:
0
0
0
TCTL4 — Timer Control Register 4
4
EDG2A
0
3
EDG1B
0
2
EDG1A
0
1
EDG0B
0
Bit 0
EDG0A
0
$008B
Read or write anytime.
EDGnB, EDGnA — Input Capture Edge Control
These eight pairs of control bits configure the input capture edge
detector circuits.
Table 14-2. Edge Detector Circuit Configuration
EDGnB
0
0
1
1
EDGnA
0
1
0
1
Configuration
Capture disabled
Capture on rising edges only
Capture on falling edges only
Capture on any edge (rising or falling)
Technical Data
238
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor