MC912D60ACPVE8 Datasheet, PDF (422/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Electrical Specifications
Num
Table 20-15. SPI Timing
(V_DD = 5.0 Vdc ±10%, V_SS = 0 Vdc, T_A = T_L to T_H , 200 pF load on all SPI pins)⁽¹⁾
Function
Symbol
Min
Max
Operating Frequency
Master
Slave
f_op
f_eclk/256
4
f_eclk/256
4
SCK Period
1 Master
Slave
t_sck
2
256
2
—
Enable Lead Time
2 Master
Slave
t_lead
1/2
—
1
—
Enable Lag Time
3 Master
Slave
t_lag
1/2
—
1
—
Clock (SCK) High or Low Time
4 Master
Slave
Sequential Transfer Delay
5 Master
Slave
Data Setup Time (Inputs)
6 Master
Slave
Data Hold Time (Inputs)
7 Master
Slave
8 Slave Access Time
9 Slave MISO Disable Time
Data Valid (after SCK Edge)
10 Master
Slave
Data Hold Time (Outputs)
11 Master
Slave
t_wsck
t_td
t_su
t_hi
t_a
t_dis
t_v
t_ho
t_cyc − 30
t_cyc − 30
1/2
1
30
30
0
30
—
—
—
—
0
0
128 t_cyc
—
—
—
—
—
—
—
1
1
50
50
—
—
Rise Time
12 Input
Output
t_ri
—
t_cyc − 30
t_ro
—
30
Fall Time
13 Input
Output
t_fi
—
t_cyc − 30
t_fo
—
30
1. All AC timing is shown with respect to 20% V_DD and 70% V_DD levels unless otherwise noted.
Unit
MHz
t_cyc
t_cyc
t_sck
t_cyc
t_sck
t_cyc
ns
ns
t_sck
t_cyc
ns
ns
ns
ns
t_cyc
t_cyc
ns
ns
ns
ns
ns
ns
ns
ns
Technical Data
422
Electrical Specifications
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor