MC912D60ACPVE8 Datasheet, PDF (268/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
BTST — Reserved for test function
BSPL — Reserved for test function
BRLD — Reserved for test function
Bit 7
6
5
4
LOOPS WOMS
RSRC
M
RESET:
0
0
0
0
SC0CR1/SC1CR1 — SCI Control Register 1
3
2
WAKE
ILT
0
0
1
Bit 0
PE
PT
0
0
$00C2/$00CA
Read or write anytime.
LOOPS — SCI LOOP Mode/Single Wire Mode Enable
0 = SCI transmit and receive sections operate normally.
1 = SCI receive section is disconnected from the RXD pin and the
RXD pin is available as general purpose I/O. The receiver input is
determined by the RSRC bit. The transmitter output is controlled
by the associated DDRS bit. Both the transmitter and the receiver
must be enabled to use the LOOP or the single wire mode.
If the DDRS bit associated with the TXD pin is set during the LOOPS
= 1, the TXD pin outputs the SCI waveform. If the DDRS bit
associated with the TXD pin is clear during the LOOPS = 1, the TXD
pin becomes high (IDLE line state) for RSRC = 0 and high impedance
for RSRC = 1. Refer to Table 15-2.
WOMS — Wired-Or Mode for Serial Pins
This bit controls the two pins (TXD and RXD) associated with the SCIx
section.
0 = Pins operate in a normal mode with both high and low drive
capability. To affect the RXD bit, that bit would have to be
configured as an output (via DDS0/2) which is the single wire
case when using the SCI. WOMS bit still affects general purpose
output on TXD and RXD pins when SCIx is not using these pins.
1 = Each pin operates in an open drain fashion if that pin is
declared as an output.
Technical Data
268
Multiple Serial Interface
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor