MC912D60ACPVE8 Datasheet, PDF (19/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Technical Data — MC68HC912D60A
List of Tables
Table
Title
Page
1-1
1-2
2-1
2-2
3-1
3-2
3-3
3-4
4-1
5-1
5-2
5-3
5-4
8-1
8-2
8-3
8-4
9-1
9-2
11-1
11-2
11-3
11-4
11-5
13-1
13-2
13-3
14-1
14-2
Device Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Development Tools Ordering Information. . . . . . . . . . . . . . . . . 28
M68HC12 Addressing Mode Summary . . . . . . . . . . . . . . . . . . 34
Summary of Indexed Operations . . . . . . . . . . . . . . . . . . . . . . . 35
MC68HC912D60A Power and Ground Connection Summary . 44
MC68HC912D60A Signal Description Summary . . . . . . . . . . . 50
MC68HC912D60A Port Description Summary . . . . . . . . . . . . . 59
Port Pull-Up, Pull-Down and Reduced Drive Summary . . . . . . 60
MC68HC912D60A Register Map . . . . . . . . . . . . . . . . . . . . . . . 62
Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Mapping Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
RFSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EXSTR Stretch Bit Definition . . . . . . . . . . . . . . . . . . . . . . . . . . 82
EEDIV Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
1K byte EEPROM Block Protection . . . . . . . . . . . . . . . . . . . . 112
Erase Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Shadow word mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Interrupt Vector Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Stacking Order on Entry to Interrupts . . . . . . . . . . . . . . . . . . . 128
Summary of STOP Mode Exit Conditions. . . . . . . . . . . . . . . . 155
Summary of Pseudo STOP Mode Exit Conditions . . . . . . . . . 155
Clock Monitor Time-Outs . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
Real Time Interrupt Rates. . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
COP Watchdog Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172
Clock A and Clock B Prescaler. . . . . . . . . . . . . . . . . . . . . . . . 212
PWM Left-Aligned Boundary Conditions . . . . . . . . . . . . . . . . 222
PWM Center-Aligned Boundary Conditions . . . . . . . . . . . . . . 222
Compare Result Output Action . . . . . . . . . . . . . . . . . . . . . . . . 238
Edge Detector Circuit Configuration . . . . . . . . . . . . . . . . . . . .238
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
List of Tables
Technical Data
19