MC912D60ACPVE8 Datasheet, PDF (296/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Freescale Interconnect Bus
16.7 MI Bus clock rate
The MI Bus clock rate is set via the SCI baud registers. To use the
MI Bus, the MCLK clock frequency that drives the SCI clock generator
must be selected to match the minimum resolution of the MI Bus logic.
This is expressed by the following formula:
MCLK = 16 • n • (2 • Push_field_bit_rate) = 16 • n • 40kHz = n • 640kHz
where ‘n’ is an integer and 20kHz is the minimum Push field bit rate for
the MI Bus. Values for MCLK could be 640kHz,1280kHz, 1920kHz, …,
n • 640kHz. The value ‘n’ is the modulus for the MI Bus baud register.
MCLK may be the output of the PLL circuit or it may be the EXTAL/2
input of the MCU. Refer to Clock Divider Chains.
16.8 SCI0/MI Bus registers
MI Bus operation is controlled by the same group of registers as is used
for the SCI. However the functions of some of the bits are modified when
in MI Bus mode. A description of the registers, as applicable to the
MI Bus function, is given here.
In MI Bus mode, bits that have no meaning are reserved by Freescale,
and are not described.
Bit 7
6
5
4
BTST
BSPL
BRLD
SBR12
RESET:
0
0
0
0
SC0BDH — MI Bus Clock Rate Control Register
3
SBR11
0
2
SBR10
0
1
SBR9
0
Bit 0
SBR8
0
High
$00C0
Bit 7
6
5
4
SBR7
SBR6
SBR5
SBR4
RESET:
0
0
0
0
SC0BDL — MI Bus Clock Rate Control Register
3
SBR3
0
2
SBR2
1
1
SBR1
0
Bit 0
SBR0
0
Low
$00C1
Technical Data
296
Freescale Interconnect Bus
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor