MC912D60ACPVE8 Datasheet, PDF (259/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
Timer Registers
If a $0000 is written into MCCNT and modulus counter while LATQ and
BUFEN in ICSYS ($AB) register are set, the input capture and pulse
accumulator registers will be latched.
With a $0000 write to the MCCNT, the modulus counter will stay at zero
and does not set the MCZF flag in MCFLG register.
If modulus mode is enabled (MODMC=1), a write to this address will
update the load register with the value written to it. The count register will
not be updated with the new value until the next counter underflow.
The FLMC bit in MCCTL ($A6) can be used to immediately update the
count register with the new value if an immediate load is desired.
If modulus mode is not enabled (MODMC=0), a write to this address will
clear the prescaler and will immediately update the counter register with
the value written to it and down-counts once to $0000.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Enhanced Capture Timer
Technical Data
259