MC912D60ACPVE8 Datasheet, PDF (267/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
Serial Communication Interface (SCI)
15.4.3 SCI Register Descriptions
Control and data registers for the SCI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. Both SCI have identical control registers
mapped in two blocks of eight bytes.
Bit 7
6
5
4
BTST
BSPL
BRLD
SBR12
RESET:
0
0
0
0
SC0BDH/SC1BDH — SCI Baud Rate Control Register
3
SBR11
0
2
SBR10
0
1
SBR9
0
Bit 0
SBR8
High
0
$00C0/$00C8
Bit 7
6
5
4
SBR7
SBR6
SBR5
SBR4
RESET:
0
0
0
0
SC0BDL/SC1BDL — SCI Baud Rate Control Register
3
SBR3
0
2
SBR2
1
1
SBR1
0
Bit 0
SBR0
Low
0
$00C1/$00C9
SCxBDH and SCxBDL are considered together as a 16-bit baud rate
control register.
Read any time. Write SBR[12:0] anytime. Low order byte must be written
for change to take effect. Write SBR[15:13] only in special modes. The
value in SBR[12:0] determines the baud rate of the SCI. The desired
baud rate is determined by the following formula:
which is equivalent to:
SCI Baud Rate = _{1--M-6----C-×}----L-B---K-R---
BR = _{1---6-----×}-----S--M-C----I-C---B--L--a--Ku---d-----R----a--t--e-
BR is the value written to bits SBR[12:0] to establish baud rate.
NOTE:
The baud rate generator is disabled until TE or RE bit in SCxCR2
register is set for the first time after reset, and/or the baud rate generator
is disabled when SBR[12:0] = 0.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Multiple Serial Interface
Technical Data
267