MC912D60ACPVE8 Datasheet, PDF (381/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

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Background Debug Mode
BKGD pin during host-to-target transmissions to speed up rising edges.
Since the target does not drive the BKGD pin during this period, there is
no need to treat the line as an open-drain signal during host-to-target
transmissions.
BDMCLK
(TARGET MCU)
HOST
TRANSMIT 1
HOST
TRANSMIT 0
PERCEIVED
START
OF BIT TIME
SYNCHRONIZATION
UNCERTAINTY
TARGET SENSES BIT
10 CYCLES
Figure 19-1. BDM Host to Target Serial Bit Timing
EARLIEST
START OF
NEXT BIT
BDMCLK
(TARGET
MCU)
HOST
DRIVE TO
BKGD PIN
TARGET MCU
SPEEDUP PULSE
PERCEIVED
START OF BIT
TIME
BKGD PIN
HIGH-IMPEDANCE
R-C RISE
HIGH-IMPEDANCE
HIGH-IMPEDANCE
10 CYCLES
10 CYCLES
HOST SAMPLES
BKGD PIN
EARLIEST
START OF
NEXT BIT
Figure 19-2. BDM Target to Host Serial Bit Timing (Logic 1)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
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Technical Data
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