MC912D60ACPVE8 Datasheet, PDF (258/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
BIT 7
6
5
4
3
2
1
BIT 0
$00B2
BIt 7
6
5
4
3
2
1
Bit 0
PA3H
$00B3
Bit 7
6
5
4
3
2
1
Bit 0
PA2H
$00B4
BIt 7
6
5
4
3
2
1
Bit 0
PA1H
$00B5
Bit 7
6
5
4
3
2
1
Bit 0
PA0H
RESET:
0
0
0
0
0
0
0
0
PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers
$00B2–$00B5
Read: any time
Write: has no effect.
These registers are used to latch the value of the corresponding pulse
accumulator when the related bits in register ICPACR ($A8) are enabled
(see Pulse Accumulators).
BIT 7
6
5
4
3
2
$00B6
BIt 15
14
13
12
11
10
$00B7
Bit 7
6
5
4
3
2
RESET:
1
1
1
1
1
1
MCCNTH/L — Modulus Down-Counter Count Register
1
BIT 0
9
Bit 8
MCCNTH
1
Bit 0
MCCNTL
1
1
$00B6, $00B7
Read: any time
Write: any time
A full access for the counter register should take place in one clock cycle.
A separate read/write for high byte and low byte will give different result
than accessing them as a word.
If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT
register will return the present value of the count register. If the RDMCL
bit is set, reads of the MCCNT will return the contents of the load
register.
Technical Data
258
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor