MC912D60ACPVE8 Datasheet, PDF (246/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Enhanced Capture Timer
This bit is cleared automatically by a write to the PAFLG register with
bit 1 set.
PAIF — Pulse Accumulator Input edge Flag
Set when the selected edge is detected at the PT7 input pin. In event
mode the event edge triggers PAIF and in gated time accumulation
mode the trailing edge of the gate signal at the PT7 input pin triggers
PAIF.
This bit is cleared by a write to the PAFLG register with bit 0 set.
Any access to the PACN3, PACN2 registers will clear all the flags in
this register when TFFCA bit in register TSCR($86) is set.
BIT 7
6
5
4
3
2
1
BIT 0
$00A2
BIt 7
6
5
4
3
2
1
Bit 0 PACN3 (hi)
$00A3
Bit 7
6
5
4
3
2
1
Bit 0 PACN2 (lo)
RESET:
0
0
0
0
0
0
0
0
PACN3, PACN2 — Pulse Accumulators Count Registers
$00A2, $00A3
Read: any time
Write: any time
The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form
the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1
in PACTL, $A0) the PACN3 and PACN2 registers contents are
respectively the high and low byte of the PACA.
When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in
PAFLG ($A1) is set.
Full count register access should take place in one clock cycle. A
separate read/write for high byte and low byte will give a different result
than accessing them as a word.
Technical Data
246
Enhanced Capture Timer
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor