MC912D60ACPVE8 Datasheet, PDF (332/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
17.13.3 msCAN12 Module Control Register 1 (CMCR1).
Bit 7
6
5
4
3
2
1
Bit 0
CMCR1 R
0
0
0
0
0
LOOPB
WUPM CLKSRC
$0101 W
RESET
0
0
0
0
0
0
0
0
LOOPB — Loop Back Self Test Mode
When this bit is set the msCAN12 performs an internal loop back
which can be used for self test operation: the bit stream output of the
transmitter is fed back to the receiver internally. The RxCAN input pin
is ignored and the TxCAN output goes to the recessive state (1). The
msCAN12 behaves as it does normally when transmitting and treats
its own transmitted message as a message received from a remote
node. In this state the msCAN12 ignores the bit sent during the ACK
slot of the CAN frame acknowledge field to insure proper reception of
its own message. Both transmit and receive interrupts are generated.
0 = Normal operation
1 = Activate loop back self test mode
WUPM — Wake-Up Mode
This flag defines whether the integrated low-pass filter is applied to
protect the msCAN12 from spurious wake-ups (see Programmable
Wake-Up Function).
0 = msCAN12 will wake up the CPU after any recessive to
dominant edge on the CAN bus.
1 = msCAN12 will wake up the CPU only in the case of dominant pulse
on the bus which has a length of at least approximately T_wup.
NOTE:
CLKSRC — msCAN12 Clock Source
This flag defines which clock source the msCAN12 module is driven from
(only for system with CGM module; see Clock System, Figure 17-7).
0 = The msCAN12 clock source is EXTALi.
1 = The msCAN12 clock source is SYSCLK, twice the frequency of
ECLK.
The CMCR1 register can be written only if the SFTRES bit in CMCR0 is
set.
Technical Data
332
MSCAN Controller
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor