MC912D60ACPVE8 Datasheet, PDF (163/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Clock Functions
Clock Divider Chains
BCSP BCSS
1:x
PHASE
LOCK
LOOP
PLLCLK
SYSCLK
÷2
T CLOCK
GENERATOR
TCLKs
TO CPU
EXTAL
EXTALi
XTAL
REDUCED
CONSUMPTION
OSCILLATOR
EXTALi
EXTALi
BCSP BCSS
0:0
BCSP BCSS
0:1
CLKSRC = 1
CLKSRC = 0
SLOW MODE
CLOCK
DIVIDER
SLWCLK
÷2
÷2
E AND P
CLOCK
GENERATOR
ECLK
PCLK
TO
BUSES,
SPI,
PWM,
ATD0, ATD1
SYNC
SYNC
MCS = 0
MCS = 1
CLKSW = 0
TO
MSCAN
MCLK
TO
SCI0, SCI1,
ECT
XCLK
TO
RTI, COP
TO CAL
CLKSW = 1
BDMCLK
TO BDM
TO CLOCK
MONITOR
Figure 11-6. Clock Generation Chain
Bus clock select bits BCSP and BCSS in the clock select register
(CLKSEL) determine which clock drives SYSCLK for the main system
including the CPU and buses. BCSS has no effect if BCSP is set. During
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Clock Functions
Technical Data
163