MC912D60ACPVE8 Datasheet, PDF (279/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
Serial Peripheral Interface (SPI)
Transfer
Begin
End
SCK (CPOL=0)
SCK (CPOL=1)
SAMPLE I
(MOSI/MISO)
CHANGE O
(MOSI pin)
CHANGE O
(MISO pin)
SEL SS (O)
(Master only)
SEL SS (I)
t_L
MSB first (LSBF=0):
LSB first (LSBF=1):
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
t_T t_I t_L
LSB Minimum 1/2 SCK
MSB
for t_T, t_l, t_L
Figure 15-5. SPI Clock Format 1 (CPHA = 1)
15.5.3 SS Output
Available in master mode only, SS output is enabled with the SSOE bit
in the SP0CR1 register if the corresponding DDRS is set. The SS output
pin will be connected to the SS input pin of the external slave device. The
SS output automatically goes low for each transmission to select the
external device and it goes high during each idling state to deselect
external devices.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
DDS7
0
0
1
1
Table 15-3. SS Output Selection
SSOE
0
1
0
1
Master Mode
SS Input with MODF Feature
Reserved
General-Purpose Output
SS Output
Slave Mode
SS Input
SS Input
SS Input
SS Input
Multiple Serial Interface
Technical Data
279