MC912D60ACPVE8 Datasheet, PDF (388/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

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• The ADDRESS register is temporary storage for BDM commands.
• The CCRSAV register preserves the content of the CPU12 CCR
while BDM is active.
The only registers of interest to users are the STATUS register and the
CCRSAV register. The other BDM registers are only used by the BDM
firmware to execute commands. The registers are accessed by means
of the hardware READ_BD and WRITE_BD commands, but should not
be written during BDM operation (except the CCRSAV register which
could be written to modify the CCR value).
19.4.5.1 STATUS
The STATUS register is read and written by the BDM hardware as a
result of serial data shifted in on the BKGD pin.
Read: all modes.
Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,
BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register
is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the
INSTRUCTION register is a one. A user would never write ones to bits
3 through 5 because these bits are only used by BDM firmware.
BIT 7
6
5
4
3
2
1
ENBDM BDMACT ENTAG
SDV
TRACE CLKSW
-
RESET:
0
1
0
0
0
0
0
(NOTE 1)
RESET:
0
0
0
0
0
0
0
STATUS— BDM Status Register⁽¹⁾
1. ENBDM is set to 1 by the firmware in Special Single Chip mode.
BIT 0
-
0
0
Special Sin-
gle Chip
& Periph
All other
modes
$FF01
ENBDM — Enable BDM (permit active background debug mode)
0 = BDM cannot be made active (hardware commands still
allowed).
1 = BDM can be made active to allow firmware commands.
Technical Data
388
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MC68HC912D60A — Rev. 3.1
Freescale Semiconductor