MC912D60ACPVE8 Datasheet, PDF (334/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
17.13.5 msCAN12 Bus Timing Register 1 (CBTR1).
CBTR1 R
$0103 W
RESET
Bit 7
SAMP
0
6
5
4
3
2
1
Bit 0
TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10
0
0
0
0
0
0
0
SAMP — Sampling
This bit determines the number of samples of the serial bus to be
taken per bit time. If set three samples per bit are taken, the regular
one (sample point) and two preceding samples, using a majority rule.
For higher bit rates SAMP should be cleared, which means that only
one sample will be taken per bit.
0 = One sample per bit.
1 = Three samples per bit.⁽¹⁾
TSEG22 – TSEG10 — Time Segment
Time segments within the bit time fix the number of clock cycles per
bit time, and the location of the sample point. (See Figure 17-8)
Table 17-7. Time segment syntax
SYNC_SEG
Transmit point
Sample point
System expects transitions to occur on the
bus during this period.
A node in transmit mode will transfer a new
value to the CAN bus at this point.
A node in receive mode will sample the bus
at this point. If the three samples per bit
option is selected then this point marks the
position of the third sample.
Time segment 1 (TSEG1) and time segment 2 (TSEG2) are
programmable as shown in Table 17-8.
Technical Data
334
1. In this case, PHASE_SEG1 must be at least two time quanta.
MSCAN Controller
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor