MC912D60ACPVE8 Datasheet, PDF (438/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Appendix: Changes from MC68HC912D60
22.2.1.3 Flash Programming Procedure
Programming of the flash is greatly simplified over previous HC12s. The
read / verify / re-pulse programming algorithm is replaced by a much
simpler method.
22.2.1.4 Flash Programming Time
The most significant change resulting from the new flash technology is
that the bulk erase and program times are now fixed. The erase time is
at least twice as fast while the word programming time is at least 20%
faster.
22.2.1.5 Flash External Programming Voltage
The new flash does not require an external high voltage supply. All
voltages required for programming and erase are now generated
internally. Pin 97 (112 QFP) or pin 71 (80 QFP) is now a test pin for the
flash arrays. Applying 12V to this pin can damage the device. On early
production devices it is recommended that this pin is not connected
within the application, but it may be connected to VSS or 5.5V max
without issue.
22.2.2 EEPROM
22.2.2.1 EEPROM Architecture
Like the flash, the EEPROM is also made from this new NVM
technology. The architecture and basic programming and erase
operations are unchanged. However, there is a new optional
programming method that allows faster programming of the EEPROM.
22.2.2.2 EEPROM Clock Source and Pre-scaler
The first major difference on the new EEPROM is that it requires a
constant time base source to ensure secure programming and erase
operations. The clock source that is going to drive the clock divider input
is the external clock input, EXTALi. The divide ratio from this source has
Technical Data
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Appendix: Changes from MC68HC912D60
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor