MC912D60ACPVE8 Datasheet, PDF (300/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Freescale Interconnect Bus
OR — Bit Error Flag
0 = No bit error has been detected.
1 = A bit error has been detected.
This bit is set when a push field bit value on the MI Bus does not
match the bit value that was sent. This is known as an MI Bus bit
error. OR does not generate an interrupt request in MI Bus mode.
NF — Noise Error Flag
0 = No noise detected.
1 = Noise detected.
This bit is set when noise is detected on the receive line during an
MI Bus pull field.
Bit 7
6
5
4
3
2
1
Bit 0
SCSWAI
MIE
MDL1
MDL0
0
0
0
RAF
RESET:
0
0
0
0
0
0
0
0
SC0SR2 — MI Bus Status Register 2
$00C5
Read anytime. Write has no meaning or effect.
SCSWAI — Serial Communications Interface Stop in WAIT Mode
0 = SCI clock operates normally.
1 = Halt SCI clock generation when in WAIT mode.
MIE — Freescale Interface Bus (MI Bus) Enable
0 = The SCI functions normally.
1 = MI Bus is enabled for this subsystem.
When MIE is set, the SCI0 registers, bits and pins assume the
functionality required for MI Bus.
MDL1, MDL0 — MI Bus delay select
These bits are used to set up the delay for the start of the NRZ receive
for MI Bus operation as shown (for a 20kHz bit rate) in the following
table.
Technical Data
300
Freescale Interconnect Bus
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor