MC912D60ACPVE8 Datasheet, PDF (184/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Oscillator
12.4.2 MC68HC912D60C Oscillator Circuit Specifications
12.4.2.1 Negative Resistance Margin
Negative Resistance Margin (NRM) is a figure of merit commonly used
to qualify an oscillator circuit with a given resonator. NRM is an indicator
of how much additional resistance in series with the resonator is
tolerable while still maintaining oscillation. This figure is usually expected
to be a multiple of the nominal "maximum" rated ESR of the resonator to
allow for variation and degradation of the resonator.
Currently, many systems are optimized for NRM by adjusting the load
capacitors until NRM is maximized. This method may not achieve the
best overall NRM because the optimization method is empirical and not
analytical. That is, the method only achieves the best NRM for the
particular sample set of microcontrollers, resonators, and board values
tested. The figure below shows the anticipated NRM for a nominal 4MHz
resonator given the expected process variance of the microcontroller
(D60A), board, and crystal (excluding ESR). In this case, the value of
load capacitors providing the optimum NRM for a best-case situation
yield an unacceptable NRM for a worst-case situation (the slope of the
NRM vs. capacitance curve is very steep, indicating severe sensitivity to
small variations). If the NRM optimization happened to be performed on
a best-case sample set, there could be unexpected sensitivity at worst-
case.
Negative Resistance Margin vs. Capacitance
1000
WCS
TYP
100
TYP
BCS
Technical Data
184
10
8 10 13 15 18 22 27 33 39 47 56 68
Capacitance
Oscillator
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor