MC912D60ACPVE8 Datasheet, PDF (352/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
• WAIT is executed (if the ASWAI bit is activated)
• STOP is executed.
The MCU can discover when result data is available in the result
registers with an interrupt on sequence complete or by polling the
conversion complete flags
• The SCF bit is set after the completion of each sequence.
• The CCF bit associated with each result register is set when that
register is loaded with result data.
NOTE:
ATD conversion modes should not be confused with MCU operating
modes such as STOP, WAIT, IDLE, RUN, DEBUG, and SPECIAL (test)
modes or with module defined operating modes such as power down,
fast flag clear, 8-bit resolution, 10-bit resolution, interrupt enable, clock
prescaler setting, and freeze modes; and finally do not confuse with
module result data formats such as right justify mode and left justify
mode.
18.4 Functional Description
18.4.1 Analog Input Multiplexer
The analog input multiplexer selects one of the 8 external analog input
channels to generate an analog sample. The input analog signals are
unipolar and must fall within the potential range of VSSA to VDDA
(analog electronics supply potentials).
18.4.2 Sample Buffer Amplifier
A sample amplifier is used to buffer the input analog signal so that a
storage node can be quickly charged to the sample potential.
Technical Data
352
Analog-to-Digital Converter
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor