MC912D60ACPVE8 Datasheet, PDF (386/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

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The external host should delay about 32 target BDMCLK cycles after the
data portion of firmware write commands to allow BDM firmware to
complete the requested write operation before a new serial command
disturbs the BDM SHIFTER register.
The external host should delay about 64 target BDMCLK cycles after a
TRACE1 or GO command before starting any new serial command. This
delay is needed because the BDM SHIFTER register is used as a
temporary data holding register during the exit sequence to user code.
BDM logic retains control of the internal buses until a read or write is
completed. If an operation can be completed in a single cycle, it does not
intrude on normal CPU12 operation. However, if an operation requires
multiple cycles, CPU12 clocks are frozen until the operation is complete.
19.4.4 BDM Lockout
The access to the MCU resources by BDM may be prevented by
enabling the BDM lockout feature. When enabled, the BDM lockout
mechanism prevents the BDM from being active. In this case the BDM
ROM is disabled and does not appear in the MCU memory map.
BDM lockout is enabled by clearing NOBDML bit of EEMCR register.
The NOBDML bit is loaded at reset from the SHADOW byte of EEPROM
module. Modifying the state of the NOBDML and corresponding
EEPROM SHADOW bit is only possible in special modes.
Please refer to EEPROM Memory for NOBDML information.
19.4.4.1 Enabling BDM lockout
Enabling the BDM lockout feature is only possible in special modes
(SMODN=0) and is accomplished by the following steps.
1. Remove the SHADOW byte protection by clearing SHPROT bit in
EEPROT register.
2. Clear NOSHB bit in EEMCR register to make the SHADOW byte
visible at $0FC0.
3. Program bit 7 of the SHADOW byte like a regular EEPROM
location at address $0FC0 (write $7F into address $0FC0). Do not
Technical Data
386
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MC68HC912D60A — Rev. 3.1
Freescale Semiconductor