MC912D60ACPVE8 Datasheet, PDF (280/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Multiple Serial Interface
15.5.4 Bidirectional Mode (MOMI or SISO)
In bidirectional mode, the SPI uses only one serial data pin for external
device interface. The MSTR bit decides which pin to be used. The MOSI
pin becomes serial data I/O (MOMI) pin for the master mode, and the
MISO pin becomes serial data I/O (SISO) pin for the slave mode. The
direction of each serial I/O pin depends on the corresponding DDRS bit.
When SPE=1
Master Mode
MSTR=1
Slave Mode
MSTR=0
Normal
Mode
SPC0=0
Serial Out
MO
SPI
DDS5
Serial In
MI
SWOM enables open drain output.
Serial In
SI
SPI
DDS4
Serial Out
SO
SWOM enables open drain output.
Bidirectional
Mode
SPC0=1
Serial Out
SPI
Serial In
DDS5
MOMI
PS4
SWOM enables open drain output. PS4 becomes GPIO.
Serial In
SPI
Serial Out
DDS4
PS5
SISO
SWOM enables open drain output. PS5 becomes GPIO.
Figure 15-6. Normal Mode and Bidirectional Mode
15.5.5 Register Descriptions
Control and data registers for the SPI subsystem are described below.
The memory address indicated for each register is the default address
that is in use after reset. For more information refer to Operating Modes
and Resource Mapping.
Bit 7
6
5
SPIE
SPE
SWOM
RESET:
0
0
0
SP0CR1 — SPI Control Register 1
4
MSTR
0
3
CPOL
0
Read or write anytime.
2
CPHA
1
Technical Data
280
Multiple Serial Interface
1
SSOE
0
Bit 0
LSBF
0
$00D0
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor