MC912D60ACPVE8 Datasheet, PDF (124/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Resets and Interrupts
RESET:
Bit 7
1
1
6
5
4
3
2
1
Bit 0
1
PSEL5 PSEL4 PSEL3 PSEL2 PSEL1
0
1
1
1
0
0
1
0
HPRIO — Highest Priority I Interrupt
$001F
Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.
To give a maskable interrupt source highest priority, write the low byte of
the vector address to the HPRIO register. For example, writing $F0 to
HPRIO would assign highest maskable interrupt priority to the real-time
interrupt timer ($FFF0). If an un-implemented vector address or a non-I-
masked vector address (value higher than $F2) is written, then IRQ will
be the default highest priority interrupt.
9.6 Resets
There are four possible sources of reset. Power-on reset (POR), and
external reset on the RESET pin share the normal reset vector. The
computer operating properly (COP) reset and the clock monitor reset
each has a vector. Entry into reset is asynchronous and does not require
a clock but the MCU cannot sequence out of reset without a system
clock.
9.6.1 Power-On Reset
A positive transition on V_DD causes a power-on reset (POR). An external
voltage level detector, or other external reset circuits, are the usual
source of reset in a system. The POR circuit only initializes internal
circuitry during cold starts and cannot be used to force a reset as system
voltage drops.
It is important to use an external low voltage reset circuit (for example:
MC34064 or MC33464) to prevent power transitions or corruption of
RAM or EEPROM.
Technical Data
124
Resets and Interrupts
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor