MC912D60ACPVE8 Datasheet, PDF (45/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
Signal Descriptions
NOTE: When selecting a crystal, it is recommended to use one with the lowest
possible frequency in order to minimise EMC emissions.
3.5.1.2 External Oscillator Connections
XTAL is the crystal output. The XTAL pin must be left unterminated when
an external CMOS compatible clock input is connected to the EXTAL
pin. The XTAL output is normally intended to drive only a crystal. The
XTAL output can be buffered with a high-impedance buffer to drive the
EXTAL input of another device.
EXTAL
MCU
XTAL _NC
2xE
CMOS-COMPATIBLE
EXTERNAL OSCILLATOR
Figure 3-6. External Oscillator Connections
3.5.2 E-Clock Output (ECLK)
ECLK is the output connection for the internal bus clock and is used to
demultiplex the address and data and is used as a timing reference.
ECLK frequency is equal to 1/2 the crystal frequency out of reset. The
ECLK output is turned off in single chip user mode to reduce the effects
of RFI. It can be turned on if necessary. In single-chip special mode, the
ECLK is turned ON at reset and can be turned OFF. In special peripheral
mode the ECLK is an input to the MCU. All clocks, including the ECLK,
are halted when the MCU is in STOP mode. It is possible to configure
the MCU to interface to slow external memory. ECLK can be stretched
for such accesses.
3.5.3 Reset (RESET)
An active low bidirectional control signal, RESET, acts as an input to
initialize the MCU to a known start-up state. It also acts as an open-drain
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Pinout and Signal Descriptions
Technical Data
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