MC912D60ACPVE8 Datasheet, PDF (327/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Programmer’s Model of Message Storage
ADDR⁽¹⁾
REGISTER
R/W BIT 7
6
5
4
3
2
$01x0
IDR0
R
ID10 ID9 ID8 ID7 ID6 ID5
W
$01x1
$01x2
$01x3
IDR1
IDR2
IDR3
R
ID2 ID1 ID0 RTR IDE(0)
W
R
W
R
W
Figure 17-12
1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.
1 BIT 0
ID4 ID3
17.12.2 Identifier Registers (IDRn)
The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29
bits (ID28–ID0) for the extended format. ID10/28 is the most significant
bit and is transmitted first on the bus during the arbitration procedure.
The priority of an identifier is defined to be highest for the smallest binary
number.
SRR — Substitute Remote Request
This fixed recessive bit is used only in extended format. It must be set
to 1 by the user for transmission buffers and will be stored as received
on the CAN bus for receive buffers.
IDE — ID Extended
This flag indicates whether the extended or standard identifier format
is applied in this buffer. In the case of a receive buffer the flag is set
as being received and indicates to the CPU how to process the buffer
identifier registers. In the case of a transmit buffer the flag indicates to
the msCAN12 what type of identifier to send.
0 = Standard format (11-bit)
1 = Extended format (29-bit)
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
MSCAN Controller
Technical Data
327