MC912D60ACPVE8 Datasheet, PDF (371/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Analog-to-Digital Converter
ATD Registers
Table 18-10. Multichannel Mode Result Register Assignment (MULT=1) (Continued)
8 channel conversion, External channels (S8C = 1, SC = 0)
CC
0
0
0
0
CB
0
0
1
1
CA
0
1
0
1
ADR0
AN0
AN1
AN2
AN3
ADR1
AN1
AN2
AN3
AN4
ADR2
AN2
AN3
AN4
AN5
ADR3
AN3
AN4
AN5
AN6
ADR4
AN4
AN5
AN6
AN7
ADR5
AN5
AN6
AN7
AN0
ADR6
AN6
AN7
AN0
AN1
ADR7
AN7
AN0
AN1
AN2
1
0
0
AN4
AN5
AN6
AN7
AN0
AN1
AN2
AN3
1
0
1
AN5
AN6
AN7
AN0
AN1
AN2
AN3
AN4
1
1
0
AN6
AN7
AN0
AN1
AN2
AN3
AN4
AN5
1
1
1
AN7
AN0
AN1
AN2
AN3
AN4
AN5
AN6
8 channel conversion, Internal Sources (S8C = 1, SC = 1)
CC
0
0
0
0
CB
0
0
1
1
CA
0
1
0
1
ADR0
ADR1
VRH
ADR2
VRH
VRL
ADR3
VRH
VRL
MID
ADR4
VRH
VRL
MID
ADR5
VRL
MID
ADR6
MID
ADR7
1
0
0
VRH
VRL
MID
1
0
1
VRL
MID
VRH
1
1
0
MID
VRH
VRL
1
1
1
VRH
VRL
MID
Shaded cells are reserved
MID = (VRH + VRL) / 2
NOTES:
1) For compatibility with the 68HC912D60, CA, CB, CC bits must be ‘0’ where masked on the 68HC912D60. This is
shown above in bold text.
2) When MULT = 0, all four bits (SC, CC, CB, and CA) must be specified and a conversion sequence consists of four
or eight consecutive conversions of the single specified channel.
3) When S8C = 0 and S1C = 1, all four bits (SC, CC, CB, and CA) must be specified and a conversion sequence consists
of one conversion of the single specified channel.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Analog-to-Digital Converter
Technical Data
371