MC912D60ACPVE8 Datasheet, PDF (161/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Clock Functions
Limp-Home and Fast STOP Recovery modes
Bit 7
6
5
0
0
SLDV5
RESET:
0
0
0
SLOW — Slow mode Divider Register
4
SLDV4
0
3
SLDV3
0
2
SLDV2
0
1
SLDV1
0
Bit 0
SLDV0
0
$003E
Read and write anytime.
A write to this register changes the SLWCLK frequency with minimum
delay (less than one SLWCLK cycle), thus allowing immediate tune-
up of the performance versus power consumption for the modules
using this clock. The frequency divide ratio is 2 times (SLOW), hence
the divide range is 2 to 126 (not on first pass products). When
SLOW = 0, the divider is bypassed. The generation of E, P and
M clocks further divides SLWCLK by 2. Hence, the final ratio of Bus
to EXTALi Frequency is programmable to 2, 4, 8, 12, 16, 20, ..., 252,
by steps of 4. SLWCLK is a 50% duty cycle signal.
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
Clock Functions
Technical Data
161