MC912D60ACPVE8 Datasheet, PDF (344/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

MSCAN Controller
Bit 7
6
5
4
3
2
1
Bit 0
CIDAR0 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0110
W
CIDAR1 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0111
W
CIDAR2 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0112
W
CIDAR3 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0113
W
RESET
–
–
–
–
–
–
–
–
Bit 7
6
5
4
3
2
1
Bit 0
CIDAR4 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0118
W
CIDAR5 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$0119
W
CIDAR6 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$011A
W
CIDAR7 R
AC7
AC6
AC5
AC4
AC3
AC2
AC1
AC0
$011B
W
RESET
–
–
–
–
–
–
–
–
AC7 – AC0 — Acceptance Code Bits
AC7 – AC0 comprise a user defined sequence of bits with which the
corresponding bits of the related identifier register (IDRn) of the
receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
NOTE: The CIDAR0–7 registers can only be written if the SFTRES bit in
CMCR0 is set.
Technical Data
344
MSCAN Controller
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor