MC912D60ACPVE8 Datasheet, PDF (50/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Pinout and Signal Descriptions
3.5.13 Inverted ECLK (ECLK)
The ECLK pin (PE7) can be used to latch the address for de-
multiplexing. It has the same behavior as the ECLK, except is inverted.
In expanded modes this pin is used to enable the drive control of external
buses during external reads. Use of the ECLK is controlled by the NDBE
and DBENE bits in the PEAR register.
3.5.14 Calibration reference (CAL)
The CAL pin (PE7) is the output of the Slow Mode programmable clock
divider, SLWCLK, and is used as a calibration reference. The SLWCLK
frequency is equal to the crystal frequency out of reset and always has
a 50% duty. If the DBE function is enabled it will override the enabled
CAL output. The CAL pin output is disabled by clearing CALE bit in the
PEAR register.
3.5.15 Clock generation module test (CGMTST)
The CGMTST pin (PE6) is the output of the clocks tested when CGMTE
bit is set in PEAR register. The PIPOE bit must be cleared for the clocks
to be tested.
3.5.16 TEST
This pin is used for factory test purposes. It is recommended that this
pin is not connected in the application, but it may be bonded to 5.5 V max
without issue. Never apply voltage higher than 5.5 V to this pin.
Pin Name
EXTAL
XTAL
RESET
Table 3-2. MC68HC912D60A Signal Description Summary
Pin Number
80-pin 112-pin
35
47
36
48
34
46
Description
Crystal driver and external clock input pins.
An active low bidirectional control signal, RESET acts as an input to
initialize the MCU to a known start-up state, and an output when COP or
clock monitor causes a reset.
Technical Data
50
Pinout and Signal Descriptions
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor