MC912D60ACPVE8 Datasheet, PDF (105/460 Pages) Freescale Semiconductor, Inc – MC68HC912D60A MC68HC912D60C MC68HC912D60P Technical Data

Technical Data — MC68HC912D60A
Section 8. EEPROM Memory
8.1 Contents
8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
8.3 EEPROM Selective Write More Zeros . . . . . . . . . . . . . . . . . . 106
8.4 EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . .107
8.5 EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . 108
8.6 Program/Erase Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.7 Shadow Word Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
8.8 Programming EEDIVH and EEDIVL Registers. . . . . . . . . . . . 116
8.2 Introduction
The MC68HC912D60A EEPROM nonvolatile memory is arranged in a
16-bit configuration. The EEPROM array may be read as either bytes,
aligned words or misaligned words. Access times are one bus cycle for
byte and aligned word access and two bus cycles for misaligned word
operations.
Programming is by byte or aligned word. Attempts to program or erase
misaligned words will fail. Only the lower byte will be latched and
programmed or erased. Programming and erasing of the user EEPROM
can be done in normal modes.
Each EEPROM byte or aligned word must be erased before
programming. The EEPROM module supports byte, aligned word, row
(32 bytes) or bulk erase, all using the internal charge pump. The erased
state is $FF. The EEPROM module has hardware interlocks which
protect stored data from corruption by accidentally enabling the
MC68HC912D60A — Rev. 3.1
Freescale Semiconductor
EEPROM Memory
Technical Data
105